Production Grade Firmware // SYSTEM_04 // MECHATRONICS

Autonomous Floor
Cleaning Robot Architecture

An embedded systems case study featuring real-time collision aversion, state-machine driven pathfinding navigation, and register-optimized telemetry processing for custom multi-axis hardware platforms.

Role
Lead Systems Eng.
Duration
Academic Term
Category
Robotics & IoT
Platform
ATmega Silicon
Firmware
C++ (.ino)
Hardware Matrix
8-Bit Core
Status
Validated
Pipeline
GitHub ↗

01 // STRUCTURAL DIRECTIVE

Project Context

The Autonomous Floor Cleaning Robot is a custom mechatronic setup engineered to perform path navigation and surface sweeping loops. It bypasses the need for high-compute microprocessing boards by utilizing efficient, low-overhead firmware architectures.

Built directly from circuit level to structural casing, the system manages incoming data streams from distance sensor arrays using non-blocking timer triggers. By checking environmental variations through real-time state trees, the vehicle applies deterministic correction maneuvers ideal for handling unmapped layouts.

02 // THE ENGINEERING CRUCIBLE

Problem Statement

Kinematic Collision Risk

Standard blind execution loops often cause hard impacts against moving room hazards, requiring responsive fallback loops to adjust navigation profiles safely.

Signal Echo & Phase Jitters

Acoustic pulse cancellation and external infrared noise introduce severe tracking interference, creating loop errors if data isn't properly debounced.

Constrained Allocations

Running multi-stage choice trees on limited 8-bit registers requires careful code optimization to prevent memory limits or stack overflows.

03 // STRATEGIC BLUEPRINT

Technical Objectives

[OBJ_01]

Continuous Scanning

Deploy non-blocking background read cycles to check environmental space without stopping active movement paths.

[OBJ_02]

H-Bridge Matching

Calibrate duty cycles directly on controller pins to enable reliable straight runs and clean turning transitions.

[OBJ_03]

Low-BOM Layout

Maximize performance metrics while using budget-friendly microcontrollers and standard peripheral sensors.

[OBJ_04]

Automatic Corner Release

Build reactive choice sequences to pull the robot out of unexpected physical traps or dead ends autonomously.

04 // MECHATRONICS LAYER SPECS

Hardware Layer Deep-Dive

CENTRAL COMPUTE U1

Microcontroller Core

Orchestrates the primary asynchronous loop, handles raw signal debouncing, and generates independent PWM channels for velocity control.

Architecture: 8-Bit AVR Processing
Operational Clock: 16 MHz Crystal
Interface Strategy: Low-Level Timers
ACOUSTIC TELEMETRY SEN1

Ultrasonic Arrays (HC-SR04)

Calculates spatial distance lines using Time-of-Flight sound reflections to build a structural barrier map ahead of the platform.

Frequency Node: 40 kHz Sound Pulses
Scanning Bounds: 2cm – 400cm Thresholds
Aperture Target: 15° Directional Cone
PROXIMITY RAY ARRAY SEN2

Infrared Sensor Array

Provides quick digital edge triggers to cover lateral areas outside the narrow acoustic beam vector.

Output Node: Binary Status Tracking
Response Speed: Sub-millisecond Read Logic
Calibration: On-Board Potentiometers
INDUCTIVE ISOLATION DRV1

L298N Dual H-Bridge Platform

Isolates sensitive logic lines from inductive motor draw, safely distributing power to twin drive tracks.

Current Max: 2.0A Continuous Per Line
Protection Strategy: Flyback Diode Array
Control Mapping: Dual Channel PWM Enablers
BUS ISOLATION PWR1

Li-Ion Power Subsystem

High-capacity battery configurations deployed with independent regulator lines to filter motor ripple noise out of processing circuits.

Chemistry Profile: 18650 Cell Balancing
Bus Configuration: Dual 5V Logic / 12V Drive
Filtering Strategy: Decoupling Electrolytics
KINEMATIC ACTUATION MOT1-2

High-Torque Geared DC Motors

Delivers steady rotational force across varying surface transitions, maintaining predictable platform tracking over time.

Drive Layout: Differential Two-Wheel Setup
Torque Control: Step Duty Cycle Balancing
Caster Nodes: Passive Pivot Center Assembly
05 // SIGNAL COHERENCE

Firmware & System Architecture

System Data Processing Loop

DATA SUBSTRATE HC-SR04 & IR Diode Array Inputs
DEBOUNCE FILTER Register Validation & Pin Buffering
STATE CONTROL Dynamic Direction Pathfinding Trees
ACTUATION LINE PWM Duty Cycles dispatched to H-Bridge
Architectural Logic Strategy: The device software relies entirely on asynchronous tracking windows. This design bypasses heavy operating system layers, guaranteeing responsive motor speed corrections when obstacles are detected.
06 // TIME CONVERSION SCHEMAS

Main Run Loop Lifecycle

01 //

Boot Config & Register Allocation

Configures I/O pin states, sets up timer presets for PWM, and assigns initial safety boundaries.

02 //

Ultrasonic Interrogation Wave

Fires a 10-microsecond trigger pulse to capture real-time distance metrics via low-latency hardware counter checks.

03 //

Telemetry Boundary Verification

Compares raw echo tracking vectors against safe thresholds to quickly flag oncoming hazards.

04 //

Adaptive Correction Sequences

When obstacles block the forward path, the logic alters individual motor tracks, executing a sharp pivot away from the barrier.

05 //

Velocity Output Dispatch

Applies calculated power levels to the driver control registers, keeping platform transitions smooth and controlled.

07 // SYSTEM FUNCTION ARRAYS

Feature Showcase

[FUNC_01]

Real-Time Aversion Matrix

Monitors physical environment boundaries continuously to reliably adjust drive behaviors before contact occurs.

[FUNC_02]

Differential Traction Steering

Enables high-efficiency rotational turning profiles, reducing wheel drag across tricky carpet-to-hardwood flooring transitions.

[FUNC_03]

Asynchronous Logic Loop

Leverages non-blocking check loops to execute sensor sweeping routines without halting motor propulsion cycles.

[FUNC_04]

Hardware Power Separation

Features split power rails that shield sensitive microcontroller boards from high-amp motor feedback spikes.

[FUNC_05]

Fallback Escape Sequences

Monitors for potential trap states, automatically executing reverse-and-pivoting paths to free the robot from tight corners.

[FUNC_06]

Modular Frame Geometry

Built with an balanced chassis layout that lowers the center of gravity while keeping components accessible for quick updates.

08 // MATH MATRICES

Sensor Interfacing & Conversion Calculations

Ultrasonic Echo Time-of-Flight Calculus

The logic driver converts raw acoustic return times into structural space metrics. The distance calculation relies on standard high-speed sound velocities:

Distance = (Measured Pulse Travel Time × 0.0343) / 2
Reflection Limits: Irregular layout corners or dampening fabrics can weaken echo returns, leading to brief pulse scattering.
Firmware Patch: Runs values through an integrated multi-step comparison window to filter out single-point sensor errors cleanly.
09 // DRIVE CONVERSIONS

Motor Steering Processing Matrix

Direction adjustments balance relative power levels applied to the H-Bridge lines. Manipulating polarity combinations allows the vehicle to spin inside tight spaces efficiently.

State Node Left/Right Pins Duty Value
FORWARD HIGH / HIGH 85% Output
PIVOT_LEFT LOW / HIGH 100% Max Torque
REVERSE LOW / LOW 70% Low Ripple
10 // TREE STRUCTURES

Autonomous Navigation Tree Logic

The choice sequencer prioritizes clear space paths. When obstacle distances fall below safe minimum markers, the background checks halt linear runs to prioritize defensive course changes.

// Conditional State Tree
if (readUltrasonicDistance() < 20) {
executeEscapePivotSequence();
} else {
maintainNominalForwardVelocity();
}
11 // DEBUGGING REGISTERS

Engineering Challenges Faced

PROBLEM NODE //

Inductive Ripple Resets

Brushed DC motor starts created heavy feedback ripples, causing the core logic chip to undergo random memory drops.

MITIGATION LOGIC //

Added electrolytic filters directly across power terminals and completely separated logic buses from actuation power lines.

PROBLEM NODE //

Ultrasonic Ghost Reflections

Acoustic waves bounced off flat corner surfaces incorrectly, occasionally hiding major walls from the processing checks.

MITIGATION LOGIC //

Updated firmware algorithms to use a rolling average buffer, checking distance consistency before executing turns.

12 // VALIDATION TELEMETRY

Performance Optimization Metrics

0 ms
Blocking Loop Overhead

Removed all standard programmatic delays to maintain continuous sensor monitoring.

< 12 KB
Flash Storage Allocations

Streamlined variable structures to keep code compact and efficient on basic microchips.

100%
Logic Rail Isolation

Eliminated electrical logic faults completely during continuous high-load operations.

13 // OUTCOME PARAMETERS

Validated Metrics

08
Hardware Subsystems
04
State Allocations
100%
Avoidance Profile Accuracy
40+ Hrs
Active Bench Validation
14 // FUTURE ROADMAP PLANS

Future Engineering Iterations

// 01 / Planar LiDAR Nodes

Upgrading distance detection with high-resolution 2D laser mapping scanners to construct accurate spatial floorplans.

// 02 / ROS2 Micro-Nodes

Migrating basic navigation scripts onto standard micro-ROS setups to integrate open-source pathfinding libraries.

// 03 / High-Res Encoders

Adding optical code discs onto wheel drive shafts to track precise vehicle velocity variations directly.


SYSTEM GATEWAY INTERCONNECT

Review Code & Circuit Schematics.

Explore firmware structures, physical pin mappings, and optimization logic configurations inside the active open-source codebase.